Meet high performance, low energy demands
Through Silicon Via (TSV) interconnects have emerged to serve a wide range of 2.5D TSV and 3D TSV packaging applications and architectures that demand very high performance and functionality at the lowest energy/performance metric. To enable the use of TSVs in 2.5D/3D TSV architectures, we have developed several back-end technology platforms to enable high volume processing of TSV-bearing wafers and assembly. Amkor’s TSV wafer process begins with 300 mm wafers that have TSVs already formed. Our wafer process thins the wafers and creates back side (BS) metallization to complete the TSV interconnection. The TSV reveal and BS metallization process flow is commonly referred to as Middle-End-Of-Line (MEOL).
Amkor’s MEOL production tooling and processes include:
- Wafer support bond and de-bonding
- TSV wafer thinning
- TSV reveal and CMP
- Wafer back side passivation
- Cu redistribution as required on the interposer wafer back side
- Lead-free plating of micro-pillar and C4 interconnects
- Wafer level probe
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