填补 TSV 和传统 WLFO/FOWLP 之间的差距
备受赞誉的硅晶圆集成扇出型技术 (SWIFT®/HDFO) 减小单晶片和多晶片应用的面积和剖面，并增加 I/O 的数量及电路密度。
SWIFT® technology enables the creation of advanced 3D structures, addressing the need for increased IC integration in emerging mobile and networking applications. The distinctive characteristics of SWIFT® are due, in part, to the fine feature capabilities associated with this innovative wafer level packaging technique. This allows aggressive design rules to be applied, compared to traditional WLFO and laminate-based assemblies.
Unique SWIFT® features include:
- Polymer dielectrics
- 多晶粒和大晶粒封装
- Large body package capability
- Interconnect density down to 2/2 μm
- 铜柱晶片互连缩小至 30 微米间距
- 3D/层叠封装功能采用穿塑通孔 (TMV®) 或高铜柱
- Meets JEDEC MSL2a and MSL3 CLR and BLR requirements
Enabling Technologies For SWIFT® Packaging:
Key assembly technologies enable the creation of these distinctive SWIFT® features. Using stepper photo imaging equipment, 2/2 μm line/space features can be achieved, enabling very high-density die-to-die connections required for SoC partitioning and networking applications where 2.5D TSV would typically be used. Fine-pitch die micro bumps provide a high-density interconnect for advanced products, such as application processors and baseband devices. In addition, tall Cu pillars enable a high-density vertical interface for mounting advanced memory devices on the top of the SWIFT® structure.
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