TSV와 WLFO/FOWLP 간의 차이 연결
수상이력이 있는 당사의 Silicon Wafer Integrated Fan-out Technology (SWIFT®)은 단일 및 다중 애플리케이션을 위한 경소단박의 특성과, 향상된 I/O와 회로 집적도를 제공하도록 설계되었습니다.
The distinctive characteristics of SWIFT are due, in part, to the fine feature capabilities associated with this innovative wafer level packaging technique. This allows aggressive design rules to be applied, compared to traditional WLFO and laminate-based assemblies. In addition, SWIFT enables the creation of advanced 3D structures that address the need for increased IC integration in emerging mobile and networking applications.
SWIFT만의 고유한 특징은 다음과 같습니다.
- 고분자 기반 유전체
- Multi-die and large die 가능
- Large package body 가능
- 2μm 선폭의 interconnect 집적도 (critical for SoC partitioning applications)
- Cu pillar die interconnect down to 30 μm pitch
- 3D/Package-on-Package capability utilizing Through Mold Via (TMV®) or tall Cu pillars
- JEDEC MSL3 CLR 및 BLR 요구사항 충족
Key assembly technologies enable the creation of these distinctive SWIFT features. Using stepper photo imaging equipment, 2/2 μm line/space features can be achieved, enabling very high-density die-to-die connections required for SoC partitioning and networking applications where 2.5D TSV would typically be used. Fine-pitch die micro bumps provide a high-density interconnect for advanced products, such as application processors and baseband devices. In addition, tall Cu pillars enable a high-density vertical interface for mounting advanced memory devices on the top of the SWIFT structure.
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