TSV와 WLFO/FOWLP 간의 차이 연결

당사의 Silicon Wafer Integrated Fan-out Technology (SWIFT®/HDFO) 기술은 더 적은 공간을 차지하며 I/O와 회로 집적도를 높여 한 개 혹은 그 이상의 칩을 사용하는 어플리케이션에 적합한, 업계 수상 이력이 있는 기술입니다.

SWIFT® technology enables the creation of advanced 3D structures, addressing the need for increased IC integration in emerging mobile and networking applications. The distinctive characteristics of SWIFT® are due, in part, to the fine feature capabilities associated with this innovative wafer level packaging technique. This allows aggressive design rules to be applied, compared to traditional WLFO and laminate-based assemblies.

Unique SWIFT® features include:

  • Polymer dielectrics
  • Multi-die and large die 가능
  • Large body package capability
  • Interconnect density down to 2/2 μm
  • 최소 30μm 간격의 Cu pillar die 인터커넥트
  • Mold Via (TMV®) 또는 tall Cu pillars를 활용하는 3D/Package-on-Package 기능
  • Meets JEDEC MSL2a and MSL3 CLR and BLR requirements

Enabling Technologies For SWIFT® Packaging:

Key assembly technologies enable the creation of these distinctive SWIFT® features. Using stepper photo imaging equipment, 2/2 μm line/space features can be achieved, enabling very high-density die-to-die connections required for SoC partitioning and networking applications where 2.5D TSV would typically be used. Fine-pitch die micro bumps provide a high-density interconnect for advanced products, such as application processors and baseband devices. In addition, tall Cu pillars enable a high-density vertical interface for mounting advanced memory devices on the top of the SWIFT® structure.

Q & A

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