Bridge the gap between TSV and traditional WLFO/FOWLP
当社の Silicon Wafer Integrated Fan-out Technology（SWIFT®/HDFO）は、シングルおよびマルチチップのパッケージにおいてフットプリントとプロファイルを低減しながら、I/Oと回路密度の向上を実現します。
SWIFT® technology enables the creation of advanced 3D structures, addressing the need for increased IC integration in emerging mobile and networking applications. The distinctive characteristics of SWIFT® are due, in part, to the fine feature capabilities associated with this innovative wafer level packaging technique. This allows aggressive design rules to be applied, compared to traditional WLFO and laminate-based assemblies.
Unique SWIFT® features include:
- Polymer dielectrics
- マルチチップ、大型チップ対応
- Large body package capability
- Interconnect density down to 2/2 μm
- Cuピラーチップ接続：30 μmピッチ対応
- スルーモールドビア（TMV®）または高さのあるCuピラーを利用した3D／パッケージ・オン・パッケージ対応
- Meets JEDEC MSL2a and MSL3 CLR and BLR requirements
Enabling Technologies For SWIFT® Packaging:
Key assembly technologies enable the creation of these distinctive SWIFT® features. Using stepper photo imaging equipment, 2/2 μm line/space features can be achieved, enabling very high-density die-to-die connections required for SoC partitioning and networking applications where 2.5D TSV would typically be used. Fine-pitch die micro bumps provide a high-density interconnect for advanced products, such as application processors and baseband devices. In addition, tall Cu pillars enable a high-density vertical interface for mounting advanced memory devices on the top of the SWIFT® structure.
ご質問やお問合せはこちらまで
以下の「リクエスト」をクリックしてご連絡ください