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CadenceLIVE – シリコンバレー

Join Amkor Technology for CadenceLIVE – Silicon Valley on April 17, 2024, at the Santa Clara Convention Center in Santa Clara, California.

Jonathan Micksch, Director of R&D Design at Amkor will present “In-Design Electrical Analysis – Design Layout with Intention Versus Post-Design Modeling/Rework.”

概要：

The traditional roles of a layout designer and electrical engineer are being reassessed as advances in package design software expand to support more functionality within the layout editor application. Designers are tasked with doing more electrical considerations and trade-offs earlier in the design creation phase to support an improved electrical signal integrity and power integrity (SI/PI) final signoff verification. Electrical engineers are now requested to define the SI/PI architecture up front and then delegate the iterative electrical tuning processes to the layout designer. While this might appear to create an overlap of electrical analysis, however, the discipline of each role is differentiated by the type of deliverable.

Initially, the electrical design process was thought to be achieved through a best practice style of trace routing followed by an electrical engineer’s modeling and feedback, resulting in numerous redesign cycles. However, with the need for advanced SI/PI package performance, the focus has turned to the necessity for intentional routing strategies, which help to reduce the amount of impact the redesign rework has on the design layout, thereby reducing the overall number of detailed SI/PI performance signoff style reviews.

With today’s emphasis on creating high-performance and cost-effective advanced package design solutions, the designer and the electrical engineer will benefit from the electrical modeling guidance provided by Cadence’s in-design analysis (IDA) software tools. The simplified electrical modeling workflows that are now available for use by the designer have enabled the electrical engineer to focus more on defining future electrical IDA architecture configurations and enhance the trusted verification modeling signoff process.