Semiconductor Tales: Materials for Packaging and Saving Cost, Vol. 2
Hello to all dear readers of Amkor In Story, it’s spring now. There are flowers blooming and warm days, so I’m enjoying the spring putting away the heavy winter clothes and doing an extensive spring cleanup. I will be continuing with the story of reducing production costs from last month. The first volume looked at the material side, and this time we will learn about manufacturing process and package structure.
Maximizing the Area
Semiconductor manufacturing apparatus, in general, work 24/7, all 365 days of the year. Sometimes, there is news about a power outage in a semiconductor factory resulting in a large financial loss. The manufacturing process is so precise and sensitized, the apparatus must maintain its operational state. Thus, equipment has to be on and working all the time. If it is working with no interruptions, you have to produce more products per unit time to be able to reduce cost. So, how can you produce more?
First, one method is maximizing the area of substrate. It may sound strange, but this just means using a substrate with a large area to make a lot at the same time. The size of the final product can be from a few mm to a few tens of mm. We don’t work on individual units but make them from a strip. Generally, every process in packaging is performed by strips. Starting from wire bonding or flip chip bonding to the end of the entire manufacturing process, everything is done on a strip basis. If the strip size can be increased so more packages can be handled at once, then the process cost goes down. The figure below shows several types of a leadframe package. You can easily see that increased area results in more packages. So, the question now is, if bigger strip is better then why do we not make two or three or even four times the current size?
Simply put, that makes the packaging process much more difficult. Think of the molding process. As shown in the picture below, the epoxy molding compound (EMC) melts and fills the mold from one end to the other, and hardens at the same time. Lately, the thickness of packages is decreasing, so the EMC has less volume to flow in, and it gets increasingly difficult to flow and fill every space. To solve this problem, a new EMC has to be developed and molding equipment must be improved accordingly.
Solving the molding problem is not the end, either. Larger strips can cause increased warpage. Increased warpage means more difficult processing to add solder balls or cut off items from each package. However, every effort leads to more competitive prices, so the research continues.
Most of the packaging cost comes from substrate. The never-ending work to reduce material cost does not stop at lowering the price for substrate – in fact, now it does away with substrate altogether.
Without a substrate from either a domestic or foreign supplier, using a redistribution layer (RDL) process allows the packaging company to make its own substrate. We call this type of package Wafer Level Packaging (WLP). Instead of a pre-preg or core, we can replace the existing laminate substrate with a few µm-thick RDL and passivation. And to follow the trend of increasing I/O sockets, there is more interest in Fan-Out WLP (FOWLP) that is larger in size than a chip.
Since the FOWLP does not have a substrate, we can expect to reduce production costs. In addition to eliminating the cost of the substrate, we can omit the interconnections between the chip and the substrate, like copper (Cu) pillars or solder bumps in a flip chip chip scale packaging (fcCSP). We can also reduce the package’s thickness because there is no substrate. As an addition benefit, no thick insulator (pre-preg, core) in the substrate means we can expect an improved radiation effect.
Eliminating a substrate means that substrate suppliers have to worry about survival. As a result, domestic and foreign suppliers are now developing Panel FOWLPs to compete with FOWLP, which has a limitation in the wafer size – the basic unit of the process. Currently, the wafer is 12 inches in diameter, and practically speaking, it cannot get bigger. Unlike WLP with its limited wafer size, Panel FOWLP uses a printed circuit board (PCB) substrate for larger area than a wafer. In the picture below, the packaging can be done in three times the area of 12-in. wafer. Since a square panel is better at utilizing the area than a circular wafer, it will have better price competitiveness than WLP – if it can solve the problems that may occur during manufacturing.
In these two issues, we have seen several research efforts to reduce the production cost in packaging. It is human nature to look for a better price, even by a tiny bit. Expecting better functionality and a lower price than yesterday is what people have come to expect from the electronics industry. There is no point at which it ends, but rather it is the destiny of the packaging industry to help reduce costs to meet these expectations. I hope it has been of help in understanding packaging in terms of reducing production costs.
It looks like I will have to worry about which topic to pick in the next issue once again. Quite a lot of people are showing interest in my story despite its shortcomings. See you again in the next issue with more interesting and helpful contents, then! (Replies of encouragement and suggestions are always welcomed.)
WRITTEN BY Gyuik Jeong. It is already 10 years since my ambitions lead me to Amkor. They say 10 years is enough to change the face of the earth, but I wish for my mind to stay curious and amazed at each and every project like a new recruit, so the work is always enjoyable.