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Chip-on-Chip (CoC) POSSUM™

CoC POSSUM™ is a packaging technology designed to assemble two or more dies together without the need for TSV. Amkor’s CoC POSSUM technology uses the existing infrastructures that are readily available, with minimum supplemental capital investment. In the Chip on Wafer (CoW) approach, the daughter (smaller) dies are flip-chip attached to the mother (larger) dies in the wafer format versus to the die format in CoC. Amkor has now been able to support CoC POSSUM builds for 200mm and 300mm wafers, in various applications ranging from ASIC, FPGA, MEMS, microcontrollers and memory devices.

 


Wafer Level Fan-Out (WLFO)

Wafer Level Fan-Out (WLFO) is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single die and multi die applications at lower costs. Amkor has developed the capability to produce both single die and multi die Wafer Level Fan-Out packages, including 3D configurations. Amkor’s rapid development cycle, robust assembly platform, and quick time to market continue to provide a path to rapid return on its Wafer Level Fan-Out investment.


Through Silicon Via (TSV) Solutions


Through Silicon Via (TSV) interconnects are emerging to serve a wide range of 3D packaging applications and 3D IC architectures that demand higher levels of performance and silicon integration. To enable the use of TSVs in these 3D applications, a number of back-end technology platforms are being developed or deployed for high volume processing. Amkor is focused on developing technology solutions for the back end processing of TSV based wafers.

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